Design methodology for global resonant H-tree clock distribution networks

Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two level resonant H-tree is presented, supporting the design of low power, low skew, and low jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the design of a two level resonant H-tree network, distributing a 5 GHz clock signal in a TSMC 0.18 mu m CMOS technology. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width.