Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

被引：0

作者：

Barraud, S. ^{[1
]}

Lapras, V. ^{[1
]}

Samson, M. P. ^{[2
]}

Gaben, L. ^{[1
,2
]}

Grenouillet, L. ^{[1
]}

Maffini-Alvaro, V. ^{[1
]}

Morand, Y. ^{[2
]}

Daranlot, J. ^{[1
]}

Rambal, N. ^{[1
]}

Previtalli, B. ^{[1
]}

Reboi, S. ^{[1
]}

Tabone, C. ^{[1
]}

Coquand, R. ^{[1
]}

Augendre, E. ^{[1
]}

Rozeau, O. ^{[1
]}

Hartmann, J. M. ^{[1
]}

Vizioz, C. ^{[1
]}

Arvet, C.

Pimenta-Barros, P. ^{[1
]}

Posseme, N. ^{[1
]}

Loup, V. ^{[1
]}

Comboroure, C. ^{[2
]}

Euvrard, C. ^{[1
]}

Baian, V. ^{[1
]}

Tinti, I. ^{[1
]}

Audoit, G. ^{[1
]}

Bernier, N. ^{[1
]}

Cooper, D. ^{[1
]}

Saghi, Z. ^{[1
]}

Allain, F. ^{[1
]}

Toffoli, A. ^{[1
]}

Faynot, O. ^{[1
]}

Vinet, M. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus, F-38054 Grenoble, France

[2] STMicroelectronics, 850 Rue J Monnet, F-38920 Crolles, France

来源：

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

引用

页数：4

共 36 条

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