CMOS switched-op-amp-based sample-and-hold circuit

被引：48

作者：

Dai, L ^{[1
]}

Harjani, R ^{[1
]}

机构：

[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 01期

关键词：

analog-digital conversion; charge injection; sample-and-hold circuits; switched opamp;

D O I：

10.1109/4.818927

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feedthrough error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-op-amps are designed and fabricated in a 2-mu CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated IC's and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits.

引用

页码：109 / 113

页数：5

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