A low-voltage fully differential CMOS high-speed sample-and-hold circuit

被引：0
|
作者：
Lee, TS [1 ]
Hsiao, KR [1 ]
机构：
[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Yunlin, Taiwan
来源：
PROCEEDINGS OF THE 44TH IEEE 2001 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new technique for realizing a low-voltage fully differential CMOS high-speed sample-and-hold (S/H) circuit is presented. The design consideration of the building blocks is described in detailed. Simulation results are given to demonstrate the potential advantage of the new technique.
引用
收藏
页码：235 / 238
页数：4
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