Universal masking on logic gate level

被引：17
|
作者：
Golic, JD
Menicocci, R
机构：
[1] Telecom Italia, Telecom Italia Lab, Syst Chip, I-10148 Turin, Italy
[2] Univ Roma La Sapienza, Dipartimento Ingn Elettron, I-00184 Rome, Italy
来源：
ELECTRONICS LETTERS | 2004年 / 40卷 / 09期
关键词：
D O I：
10.1049/el:20040385
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of crytographic algorithms against side-channel attacks.
引用
收藏
页码：526 / 528
页数：3
相关论文
共 50 条
  • [21] Design of Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit
    Sen, Bibhash
    Sengupta, Anik
    Dalui, Mamata
    Sikdar, Biplab K.
    53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1181 - 1184
  • [22] All-Optical Surface Plasmonic Universal Logic Gate Devices
    Nilima Gogoi
    Partha Pratim Sahu
    Plasmonics, 2016, 11 : 1537 - 1542
  • [23] All-Optical Surface Plasmonic Universal Logic Gate Devices
    Gogoi, Nilima
    Sahu, Partha Pratim
    PLASMONICS, 2016, 11 (06) : 1537 - 1542
  • [24] Novel universal threshold logic gate based on RTD and its application
    Wei, Yi
    Shen, Jizhong
    MICROELECTRONICS JOURNAL, 2011, 42 (06) : 851 - 854
  • [25] An Electrochemically Transduced XOR Logic Gate at the Molecular Level
    Liu, Yaqing
    Offenhaeusser, Andreas
    Mayer, Dirk
    ANGEWANDTE CHEMIE-INTERNATIONAL EDITION, 2010, 49 (14) : 2595 - 2598
  • [26] Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit
    Sen, Bibhash
    Sengupta, Anik
    Dalui, Mamata
    Sikdar, Biplab K.
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 613 - 620
  • [27] Moebius Circuit: Dual-Rail Dynamic Logic for Logic Gate Level Pipeline with Error Gate Search Feature
    Jeong, MyeongGyu
    Nakura, Toru
    Ikeda, Makoto
    Asada, Kunihiro
    GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 177 - 180
  • [28] Split gate MOSFETs in BiCMOS power technology for logic level gate voltage application
    Tsai, Chin-Yu
    Efland, Taylor R.
    Pendharkar, Sameer
    IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), 1999, : 85 - 88
  • [29] Gate-Level Masking under a Path-Based Leakage Metric
    Leiserson, Andrew J.
    Marson, Mark E.
    Wachs, Megan A.
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2014, 2014, 8731 : 580 - 597
  • [30] Gate-level masking under a path-based leakage metric
    Leiserson, Andrew J.
    Marson, Mark E.
    Wachs, Megan A.
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2014, 8731 : 580 - 597
12345