Universal masking on logic gate level

被引：17
|
作者：
Golic, JD
Menicocci, R
机构：
[1] Telecom Italia, Telecom Italia Lab, Syst Chip, I-10148 Turin, Italy
[2] Univ Roma La Sapienza, Dipartimento Ingn Elettron, I-00184 Rome, Italy
来源：
ELECTRONICS LETTERS | 2004年 / 40卷 / 09期
关键词：
D O I：
10.1049/el:20040385
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of crytographic algorithms against side-channel attacks.
引用
收藏
页码：526 / 528
页数：3
相关论文
共 50 条
  • [31] Universal Linear-Optical Logic Gate with Maximal Intensity Contrast Ratios
    Peng, Changnan
    Li, Jiayu
    Liao, Huimin
    Li, Zhi
    Sun, Chengwei
    Chen, Jianjun
    Gong, Qihuang
    ACS PHOTONICS, 2018, 5 (03): : 1137 - 1143
  • [32] A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design
    Mattela, Venkat
    Debroy, Sanghamitra
    Sivasubramani, Santhosh
    Acharyya, Amit
    NANOTECHNOLOGY, 2021, 32 (09)
  • [33] Universal Logic Modules Based on Double-Gate Carbon Nanotube Transistors
    Zukoski, Andrew
    Yang, Xuebei
    Mohanram, Kartik
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 884 - 889
  • [34] A Single-Device Universal Logic Gate Based on a Magnetically Enhanced Memristor
    Prezioso, Mirko
    Riminucci, Alberto
    Graziosi, Patrizio
    Bergenti, Ilaria
    Rakshit, Rajib
    Cecchini, Raimondo
    Vianelli, Anna
    Borgatti, Francesco
    Haag, Norman
    Willis, M.
    Drew, Alan J.
    Gillin, William P.
    Dediu, Valentin A.
    ADVANCED MATERIALS, 2013, 25 (04) : 534 - 538
  • [35] Simple and Universal Platform for Logic Gate Operations Based on Molecular Beacon Probes
    Park, Ki Soo
    Seo, Myung Wan
    Jung, Cheulhee
    Lee, Joon Young
    Park, Hyun Gyu
    SMALL, 2012, 8 (14) : 2203 - 2212
  • [36] DEVELOPMENT OF A USER FRIENDLY GATE-LEVEL LOGIC SIMULATOR
    STIGALL, PD
    SHIV, K
    COMPUTERS & ELECTRICAL ENGINEERING, 1987, 13 (3-4) : 147 - 167
  • [37] On the Complexity of Generating Gate Level Information Flow Tracking Logic
    Hu, Wei
    Oberg, Jason
    Irturk, Ali
    Tiwari, Mohit
    Sherwood, Timothy
    Mu, Dejun
    Kastner, Ryan
    IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, 2012, 7 (03) : 1067 - 1080
  • [38] A 3-Input Universal Logic Gate (ULG) Using A Single Electron Linear Threshold Gate (LTG)
    Rehan, Sameh Ebrahim
    2012 16TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (MELECON), 2012, : 630 - 633
  • [39] Use of the Modification of the Petri Nets Algorithm for the Logic Simulation of Gate-Level Logic Circuits
    Bulakh D.A.
    Kazennov G.G.
    Lapin A.V.
    Russian Microelectronics, 2018, 47 (7) : 522 - 525
  • [40] Universal Reversible Logic Gate Design For Low Power Computation at Nano-Scale
    Maity, Maumita
    Ghosal, Prasun
    Das, Bishwarup
    2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA), 2012, : 173 - 177
12345