Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

被引：4
|
作者：
Chang, WJ [1 ]
Ker, MD [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 30039, Taiwan
来源：
IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | 2004年
关键词：
D O I：
10.1109/IPFA.2004.1345599
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-mum and 0.25-mum CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-mum salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.
引用
收藏
页码：213 / 216
页数：4
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