Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

被引：4
|
作者：
Chang, WJ [1 ]
Ker, MD [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 30039, Taiwan
来源：
IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | 2004年
关键词：
D O I：
10.1109/IPFA.2004.1345599
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-mum and 0.25-mum CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-mum salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.
引用
收藏
页码：213 / 216
页数：4
相关论文
共 50 条
  • [41] Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors
    俞波
    王源
    贾嵩
    张钢刚
    半导体学报, 2009, (07) : 81 - 83
  • [42] Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability
    Ker, Ming-Dou
    Hu, Fang-Ling
    2007 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 36 - +
  • [43] Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors
    Yu Bo
    Wang Yuan
    Jia Song
    Zhang Ganggang
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (07)
  • [44] Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
    Ker, MD
    Chuang, CH
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (06) : 363 - 365
  • [45] Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications
    Wang, Zhixin
    Sun, Ruei-Cheng
    Liou, Juin J.
    Liu, Don-Gey
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (07) : 2588 - 2594
  • [46] Design of a dual-directional diode-triggered SCR for low voltage ESD protection
    Xu Q.
    Liang H.
    Gu X.
    IEEJ Transactions on Electronics, Information and Systems, 2020, 140 (06) : 673 - 674
  • [47] A Novel Capacitance-Coupling-Triggered SCR for Low-Voltage ESD Protection Applications
    Li, Mingliang
    Dong, Shurong
    Liou, Juin J.
    Song, Bo
    Han, Yan
    IEEE ELECTRON DEVICE LETTERS, 2010, 31 (10) : 1089 - 1091
  • [48] Novel Punch-through Diode Triggered SCR for Low Voltage ESD Protection Applications
    Bouangeune, Daoheung
    Vilathong, Sengchanh
    Cho, Deok-Ho
    Shim, Kyu-Hwan
    Leem, See-Jong
    Choi, Chel-Jong
    Journal of Semiconductor Technology and Science, 2014, 14 (06) : 797 - 801
  • [49] Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability
    Nedalgi, Dharmaray
    Siddamal, Saroja V.
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2022, 31 (11)
  • [50] A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application
    Deng, Jun
    Yang, Hongjiao
    Wang, Yang
    Zhou, Fengfeng
    Chen, Haotian
    Nie, Beibei
    Liu, Wei
    MICROELECTRONICS RELIABILITY, 2025, 168
12345