Design of 2-Bit Parallel Asynchronous Self-timed Adder and 2-Bit Parallel Adder Using Radix Adder

This paper presents design of asynchronous parallel adder by using recursive approach and comparison of various parameters such as average power, power-delay product, and number of transistors to design different adders. The parallel asynchronous self-timed adder designed using half adder along 2: 1 multiplexer requires minimum interconnection. These adders have propensity to run faster than existing adders for random data. Parallel adder based on radix method provides faster computation of sum and reduces delay which is generated by carry chain. One-bit asynchronous parallel adder is designed with 24T transistor, while 1-bit radix adder is designed with 28T. In radix-based parallel adder, firstly carry is generated and then generated carry is used in sum propagation, which provides low area. Both adders are implemented using Mentor Graphics tool on tsmc018. mod process.