JOSEPHSON 2-BIT FULL ADDER UTILIZING WIDE MARGIN FUNCTIONAL GATES

被引:6
|
作者
ICHIMIYA, Y
YAMADA, H
ISHIDA, A
机构
关键词
D O I
10.1109/TMAG.1983.1062329
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:1178 / 1181
页数:4
相关论文
共 49 条
  • [1] JOSEPHSON DUAL RAIL 2-BIT ADDER CIRCUIT UTILIZING MAGNETICALLY COUPLED OR AND GATES
    YAMADA, H
    ICHIMIYA, Y
    ISHIDA, A
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (03) : 307 - 310
  • [2] A JOSEPHSON 4-BIT FULL ADDER USING DIRECT-COUPLED FUNCTIONAL GATES
    MATHERON, G
    MIGNY, P
    SIE, O
    IEEE TRANSACTIONS ON MAGNETICS, 1985, 21 (02) : 555 - 557
  • [3] JOSEPHSON FOUR-BIT FULL ADDER USING DIRECT COUPLED FUNCTIONAL GATES.
    Matheron, G.
    Migny, Ph.
    Sie, O.
    IEEE Transactions on Magnetics, 1984, MAG-21 (02):
  • [4] Design of 2-Bit Parallel Asynchronous Self-timed Adder and 2-Bit Parallel Adder Using Radix Adder
    Kumar, Kuleen
    Sharma, Tripti
    INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND APPLICATIONS, ICICA 2016, 2018, 632 : 197 - 205
  • [5] 2-Bit Full Adder Implementation Using Single Spin Logic Paradigm
    Ghosh, Bahniman
    Ajay, A.
    JOURNAL OF LOW POWER ELECTRONICS, 2014, 10 (02) : 214 - 219
  • [6] NOVEL 2-BIT FULL ADDER DESIGN IN QUANTUM DOT CELLULAR AUTOMATA TECHNIQUE
    Nile, Pranali
    Mohite, Sayli
    Kassa, Sankit
    IIOAB JOURNAL, 2019, 10 : 167 - 173
  • [7] 2-BIT GATES ARE UNIVERSAL FOR QUANTUM COMPUTATION
    DIVINCENZO, DP
    PHYSICAL REVIEW A, 1995, 51 (02): : 1015 - 1022
  • [8] 2-BIT TRINARY FULL ADDER DESIGN BASED ON RESTRICTED SIGNED-DIGIT NUMBERS
    AHMED, JU
    AWWAL, AAS
    KARIM, MA
    OPTICS AND LASER TECHNOLOGY, 1994, 26 (04): : 225 - 228
  • [9] A JOSEPHSON 2-BIT ARITHMETIC-LOGIC UNIT
    NAKAGAWA, H
    KUROSAWA, I
    TAKADA, S
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1987, 34 (09): : 1123 - 1124
  • [10] FULL ADDER WITH ONLY TWO JOSEPHSON TUNNELING GATES PER STAGE.
    Herrell, D.J.
    IBM Technical Disclosure Bulletin, 1974, 17 (02): : 559 - 560