Extraction of Drain Current Thermal Noise in a 28 nm High-k/Metal Gate RF CMOS Technology

被引:5
|
作者
Zhang, Huaiyuan [1 ]
Niu, Guofu [1 ]
Liang, Qingqing [2 ]
Imura, Kimihiko [3 ]
机构
[1] Auburn Univ, Elect & Comp Engn Dept, Auburn, AL 36849 USA
[2] Qualcomm Inc, San Diego, CA 92121 USA
[3] MaxLinear Inc, Carlsbad, CA 92008 USA
关键词
Gate resistance; noise; RF CMOS; RESISTANCE; TRANSISTORS; MOSFETS; MODEL;
D O I
10.1109/TED.2018.2820698
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper investigates RF noise in a 28-nm replacement metal gate RF CMOS technology. The gate resistance is shown to be limited by interfacial resistance in metal gate stack. Intrinsic noise factor gamma(int)(gd0) = S-id(int)/4kTg(d0) and shot noise suppression factor k(S)(int) = S-id(int)/2qI(DS) are extracted. g(d0) from S-parameters is shown to be more accurate than from dc I-V. gamma(int)(gd0) remains less than 2, despite a large increase from 90-nm gate length, as well as a much stronger increase with V-DS. k(s)(int) shows a decrease on V-GS and a weak increase on V-DS. Of all four noise parameters, noise resistance plays the most significant role in intrinsic drain current noise extraction. Extrinsic and intrinsic noise resistance can be modeled by simple expressions.
引用
收藏
页码:2393 / 2399
页数:7
相关论文
共 50 条
  • [21] Intrinsic Dielectric Stack Reliability of a High Performance Bulk Planar 20nm Replacement Gate High-K Metal Gate Technology and Comparison to 28nm Gate First High-K Metal Gate Process
    McMahon, W.
    Tian, C.
    Uppal, S.
    Kothari, H.
    Jin, M.
    LaRosa, G.
    Nigam, T.
    Kerber, A.
    Linder, B. P.
    Cartier, E.
    Lai, W. L.
    Liu, Y.
    Ramachandran, R.
    Kwon, U.
    Parameshwaran, B.
    Krishnan, S.
    Narayanan, V.
    2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
  • [22] Gate-first high-k/metal gate stack for advanced CMOS technology
    Nara, Y.
    Mise, N.
    Kadoshima, M.
    Morooka, T.
    Kamiyama, S.
    Matsuki, T.
    Sato, M.
    Ono, T.
    Aoyama, T.
    Eimori, T.
    Ohji, Y.
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1241 - 1243
  • [23] Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors
    Ioannidis, E. G.
    Haendler, S.
    Bajolet, A.
    Pahron, T.
    Planes, N.
    Arnaud, F.
    Bianchi, R. A.
    Haond, M.
    Golanski, D.
    Rosa, J.
    Fenouillet-Beranger, C.
    Perreau, P.
    Dimitriadis, C. A.
    Ghibaudo, G.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [24] Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
    Lin, Chun-Yu
    Ker, Ming-Dou
    Chang, Pin-Hsin
    Wang, Wen-Tai
    2015 IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2015,
  • [25] A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell
    Hsiao, Woan Yun
    Mei, Chin Yu
    Shen, Wen Chao
    Chih, Yue Der
    King, Ya-Chin
    Lin, Chrong Jung
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2014, 53 (04)
  • [26] Fluorine interface treatments within the gate stack for defect passivation in 28nm high-k metal gate technology
    Drescher, Maximilian
    Naumann, Andreas
    Sundqvist, Jonas
    Erben, Elke
    Grass, Carsten
    Trentzsch, Martin
    Lazarevic, Florian
    Leitsmann, Roman
    Plaenitz, Philipp
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2015, 33 (02):
  • [27] High-k gate dielectrics for scaled CMOS technology
    Ma, TP
    SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 297 - 302
  • [28] Single metal gate on high-k gate stacks for 45nm low power CMOS
    Taylor, W. J., Jr.
    Capasso, C.
    Min, B.
    Winstead, B.
    Verret, E.
    Loiko, K.
    Gilmer, D.
    Hegde, R. I.
    Schaeffer, J.
    Luckowski, E.
    Martinez, A.
    Raymond, M.
    Happ, C.
    Triyoso, D. H.
    Kalpat, S.
    Haggag, A.
    Roan, D.
    Nguyen, J. -Y.
    La, L. B.
    Hebert, L.
    Smith, J.
    Jovanovic, D.
    Burnett, D.
    Foisy, M.
    Cave, N.
    Tobin, P. J.
    Samavedam, S. B.
    White, B. E., Jr.
    Venkatesan, S.
    2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 366 - +
  • [29] Revisited RF Compact Model of Gate Resistance Suitable for High-K/Metal Gate Technology
    Dormieu, Benjamin
    Scheer, Patrick
    Charbuillet, Clement
    Jaouen, Herve
    Danneville, Francois
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) : 13 - 19
  • [30] Dielectric breakdown in a 45 nm high-k/metal gate process technology
    Prasad, C.
    Agostinelli, M.
    Auth, C.
    Brazier, M.
    Chau, R.
    Dewey, G.
    Ghani, T.
    Hattendorf, M.
    Hicks, J.
    Jopling, J.
    Kavalieros, J.
    Kotlyar, R.
    Kuhn, M.
    Kuhn, K.
    Maiz, J.
    McIntyre, B.
    Metz, M.
    Mistry, K.
    Pae, S.
    Rachmady, W.
    Ramey, S.
    Roskowski, A.
    Sandford, J.
    Thomas, C.
    Wiegand, C.
    Wiedemer, J.
    2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 667 - +