The Scaling Issues of Subnanometer EOT Gate Dielectrics for the Ultimate Nano CMOS Technology

被引：0
|
作者：
Zhang, J. [1 ]
Wong, H. [1 ]
Filip, V. [2 ]
机构：
[1] City Univ Hong Kong, Dept Elect Engn, Tat Chee Ave, Kowloon, Hong Kong, Peoples R China
[2] Univ Bucharest, Fac Phys, 405 Atomistilor Str,POB MG 11, Magurele 077125, Romania
来源：
2017 IEEE 30TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL) | 2017年
关键词：
BAND OFFSETS; LANTHANUM; TRANSISTORS; STABILITY; DEFECTS; SILICON; FUTURE; OXIDES; LAYERS; FILMS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An overview of the state-of-the art of the ongoing research on high-k gate dielectrics for the advanced nano-CMOS technology is presented. The most promising high-k candidates for next-generation MOS devices are highlighted. The associated performance degradation and the scaling limitations of these high-k materials are also discussed and emerging solutions and optimization schemes for the subnanometer equivalent oxide thickness (EOT) technology are proposed.
引用
收藏
页码：49 / 54
页数：6
相关论文
共 50 条
  • [1] On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology
    Wong, Hei
    Iwai, Hiroshi
    MICROELECTRONIC ENGINEERING, 2015, 138 : 57 - 76
  • [2] The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics
    Wong, Hei
    Zhou, Jian
    Zhang, Jieqiong
    Jin, Hao
    Kakushima, Kuniyuki
    Iwai, Hiroshi
    NANOSCALE RESEARCH LETTERS, 2014, 9
  • [3] The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics
    Hei Wong
    Jian Zhou
    Jieqiong Zhang
    Hao Jin
    Kuniyuki Kakushima
    Hiroshi Iwai
    Nanoscale Research Letters, 9
  • [4] On the Scaling of Lanthanum Oxide Gate Dielectric Film into the Subnanometer EOT Range
    Wong, Hei
    Zhang, Jieqiong
    Feng, Xuan
    Yu, Danqun
    Iwai, Hiroshi
    Kakushima, Kuniyuki
    2016 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2016), 2016, : 36 - 39
  • [5] On the Issues of Subnanometer FOT Gate Dielectric Scaling
    Wong, Hei
    Liou, J. J.
    Wei, R. H.
    2019 8TH INTERNATIONAL SYMPOSIUM ON NEXT GENERATION ELECTRONICS (ISNE), 2019,
  • [6] Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics
    Magnone, P.
    Pace, C.
    Crupi, F.
    Giusi, G.
    MICROELECTRONICS RELIABILITY, 2007, 47 (12) : 2109 - 2113
  • [7] Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices
    Wong, Hei
    Zhang, Jieqiong
    Iwai, Hiroshi
    Kakushima, Kuniyuki
    NANOMATERIALS, 2021, 11 (08)
  • [8] Scaling of gate dielectrics for advanced CMOS applications
    Ma, TP
    PHYSICS AND CHEMISTRY OF SIO2 AND THE SI-SIO2 INTERFACE - 4, 2000, 2000 (02): : 19 - 32
  • [9] Ultimate EOT Scaling (<5Å) Using Hf-Based High-κ Gate Dielectrics and Impact on Carrier Mobility
    Ando, Takashi
    Frank, Martin M.
    Choi, Kisik
    Choi, Changhwan
    Bruley, John
    Hopstaken, Marinus
    Haight, Richard
    Copel, Matt
    Arimura, Hiroaki
    Watanabe, Heiji
    Narayanan, Vijay
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2010, 28 (01): : 115 - 123
  • [10] Gate dielectrics for ultimate CMOS technologies -: Limitations and alternative solutions
    Ghibaudo, G
    Clerc, R
    Vincent, E
    Bruyère, S
    Autran, JL
    COMPTES RENDUS DE L ACADEMIE DES SCIENCES SERIE IV PHYSIQUE ASTROPHYSIQUE, 2000, 1 (07): : 911 - 927
12345