The Scaling Issues of Subnanometer EOT Gate Dielectrics for the Ultimate Nano CMOS Technology

被引：0
|
作者：
Zhang, J. [1 ]
Wong, H. [1 ]
Filip, V. [2 ]
机构：
[1] City Univ Hong Kong, Dept Elect Engn, Tat Chee Ave, Kowloon, Hong Kong, Peoples R China
[2] Univ Bucharest, Fac Phys, 405 Atomistilor Str,POB MG 11, Magurele 077125, Romania
来源：
2017 IEEE 30TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL) | 2017年
关键词：
BAND OFFSETS; LANTHANUM; TRANSISTORS; STABILITY; DEFECTS; SILICON; FUTURE; OXIDES; LAYERS; FILMS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An overview of the state-of-the art of the ongoing research on high-k gate dielectrics for the advanced nano-CMOS technology is presented. The most promising high-k candidates for next-generation MOS devices are highlighted. The associated performance degradation and the scaling limitations of these high-k materials are also discussed and emerging solutions and optimization schemes for the subnanometer equivalent oxide thickness (EOT) technology are proposed.
引用
收藏
页码：49 / 54
页数：6
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