Detection of electron trap generation due to constant voltage stress on high-k gate stacks

被引：20

作者：

Young, C. D. ^{[1
]}

Nadkarni, S. ^{[1
]}

Heh, D. ^{[4
]}

Harris, H. R. ^{[2
]}

Choi, R. ^{[1
]}

Peterson, J. J. ^{[1
]}

Sim, J. H. ^{[1
]}

Krishnan, S. A. ^{[1
]}

Barnett, J. ^{[1
]}

Vogel, E. ^{[4
]}

Lee, B. H. ^{[3
]}

Zeitzoff, P. ^{[1
]}

Brown, G. A. ^{[1
]}

Bersuker, G. ^{[1
]}

机构：

[1] SEMATECH, 2706 Montopolis Dr, Austin, TX 78741 USA

[2] AMD, Sunnyvale, CA USA

[3] IBM Corp, Armonk, NY USA

[4] Natl Inst Stand & Technol, Gaithersburg, MD 20899 USA

来源：

2006 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 44TH ANNUAL | 2006年

关键词：

high-k; trap generation; charge pumping; trapped charge;

D O I：

10.1109/RELPHY.2006.251211

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2/HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-kappa gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-kappa stacks.

引用

页码：169 / +

页数：3

共 50 条

[21] Theoretical analysis of high-k dielectric gate stacks
Demkov, A. A.
Sharia, O.
Lee, J. K.
MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2032 - 2034
[22] High-k/Metal Gate Stacks in Gate First and Replacement Gate Schemes
Kesapragada, Sree
Wang, Rongjun
Liu, Dave
Liu, Guojun
Xie, Zhigang
Ge, Zhenbin
Yang, Haichun
Lei, Yu
Lu, Xinliang
Tang, Xianmin
Lei, Jianxin
Allen, Miller
Gandikota, Srinivas
Moraes, Kevin
Hung, Steven
Yoshida, Naomi
Chang, Chorng-Ping
2010 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE, 2010, : 256 - 259
[23] Flat-band voltage shift in metal-gate/high-k/Si stacks
Huang An-Ping
Zheng Xiao-Hu
Xiao Zhi-Song
Yang Zhi-Chao
Wang Mei
Chu, Paul K.
Yang Xiao-Dong
CHINESE PHYSICS B, 2011, 20 (09)
[24] Flat-band voltage shift in metal-gate/high-k/Si stacks
黄安平
郑晓虎
肖志松
杨智超
王玫
朱剑豪
杨晓东
Chinese Physics B, 2011, 20 (09) : 389 - 399
[25] Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions
Wu, Jun
Babadi, Aein Shiri
Jacobsson, Daniel
Colvin, Jovana
Yngman, Sofie
Timm, Rainer
Lind, Erik
Wemersson, Lars-Erik
NANO LETTERS, 2016, 16 (04) : 2418 - 2425
[26] Influence of interlayer properties on the characteristics of high-k gate stacks
Engstrom, O.
Mitrovic, I. Z.
Hall, S.
SOLID-STATE ELECTRONICS, 2012, 75 : 63 - 68
[27] Review of reliability issues in high-k/metal gate stacks
Degraeve, R.
Aoulaiche, M.
Kaczer, B.
Roussel, Ph.
Kauerauf, T.
Sahhaf, S.
Groeseneken, G.
IPFA 2008: PROCEEDINGS OF THE 15TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2008, : 239 - +
[28] Density functional theory of high-k dielectric gate stacks
Demkov, Alexander A.
Sharia, Onise
Luo, Xuhui
Lee, Jaekwang
MICROELECTRONICS RELIABILITY, 2007, 47 (4-5) : 686 - 693
[29] Different noise mechanisms in high-k dielectric gate stacks
Çelik-Butler, Z
NOISE IN DEVICES AND CIRCUITS III, 2005, 5844 : 177 - 184
[30] Interface dipole engineering in metal gate/high-k stacks
CHU Paul K
Chinese Science Bulletin, 2012, 57 (22) : 2872 - 2878

← 1 2 3 4 5 →