Optimization of EeLADA for Circuit Logic Defect Localization Using Defect Simulation

被引：0

作者：

Yeoh, B. L. ^{[1
]}

Goh, S. H. ^{[1
]}

You, G. F. ^{[1
]}

Tan, Alan ^{[1
]}

Hao, Hu ^{[1
]}

Chan, Y. H. ^{[1
]}

Zhao, Lin ^{[1
]}

Gupta, Varun ^{[1
]}

Ma, H. H. W. T. ^{[1
]}

Neo, S. P. ^{[1
]}

Ang, G. B. ^{[1
]}

Ngow, Y. T. ^{[1
]}

Lam, Jeffrey ^{[1
]}

Tay, C. C. ^{[2
]}

机构：

[1] GLOBALFOUNDRIES, Technol Dev Prod Test & Failure Anal, Singapore, Singapore

[2] Mentor Graph Corp, Wilsonville, OR USA

来源：

ISTFA 2016: CONFERENCE PROCEEDINGS FROM THE 42ND INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS | 2016年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

引用

页码：540 / 546

页数：7

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