Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

被引：13

作者：

Mertens, H. ^{[1
]}

Ritzenthaler, R. ^{[1
]}

Oniki, Y. ^{[1
]}

Gowda, P. Puttarame ^{[1
]}

Mannaert, G. ^{[1
]}

Sebaai, F. ^{[1
]}

Hikavyy, A. ^{[1
]}

Rosseel, E. ^{[1
]}

Dupuy, E. ^{[1
]}

Peter, A. ^{[1
]}

Vandersmissen, K. ^{[1
]}

Radisic, D. ^{[1
]}

Briggs, B. ^{[1
]}

Batuk, D. ^{[1
]}

Geypen, J. ^{[1
]}

Martinez-Alanis, G. ^{[1
]}

Seidel, F. ^{[1
]}

Richard, O. ^{[1
]}

Chan, B. T. ^{[1
]}

Mitard, J. ^{[1
]}

Litta, E. Dentoni ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

来源：

2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | 2022年

关键词：

D O I：

10.1109/IEDM45625.2022.10019497

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on forksheet field-effect transistors that are isolated from the substrate by bottom dielectric isolation (BDI) formed by replacing a SiGe epitaxial layer with a dielectric film while the devices are anchored to the substrate by forksheet walls. Functional unipolar forksheet devices with BDI are demonstrated for both N- and PMOS, for wall widths down to 10 nm. In addition, we describe a scheme to isolate adjacent source-drain structures by the forksheet dielectric wall. This scheme relies on increasing wall height, by means of active area patterning hard mask engineering, to compensate for wall losses in downstream process modules. Finally, self-alignment of gate cut to active is demonstrated morphologically.

引用

页数：4

共 50 条

[41] Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High-κ Dielectrics, and Metallic Source/Drain
Vinet, M.
Poiroux, T.
Licitra, C.
Widiez, J.
Bhandari, J.
Previtali, B.
Vizioz, C.
Lafond, D.
Arvet, C.
Besson, P.
Baud, L.
Morand, Y.
Rivoire, M.
Nemouchi, F.
Carron, V.
Deleonibus, S.
IEEE ELECTRON DEVICE LETTERS, 2009, 30 (07) : 748 - 750
[42] Self-Aligned Top-Gate Amorphous Zinc-Tin Oxide Thin-Film Transistor with Source/Drain Regions Doped by Al Reaction
Yang, Huan
Li, Jiye
Zhou, Xiaoliang
Lu, Lei
Zhang, Shengdong
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 653 - 657
[43] Comparison of N2 and Ar plasma treatment for source/drain formation in self-aligned top-gate amorphous InGaZnO thin film transistor
Lu, Hongjuan
Ren, Chongyang
Xiao, Xiang
Xiao, Yuxiang
Wang, Cuicui
Zhang, Shengdong
2016 23RD INTERNATIONAL WORKSHOP ON ACTIVE-MATRIX FLATPANEL DISPLAYS AND DEVICES (AM-FPD), 2016, : 131 - 134
[44] A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
Chang, KM
Chung, YH
Lin, GM
Lin, JH
Deng, CG
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (10) : 472 - 474
[45] Self-aligned top-gate amorphous oxide thin-film transistors with IZO/IGZO stacked active layer and Al reacted source/drain region
Chang, Baozhu
Deng, Xuan
Tao, Jinao
Yang, Huan
Zhang, Shengdong
2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019,
[46] A dual-gate complementary metal-oxide-semiconductor technology with novel self-aligned pocket implantation which takes advantage of elevated source/drain configurations
Sugihara, K
Miura, N
Furukawa, T
Nakahata, T
Oishi, T
Maruno, S
Abe, Y
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2001, 40 (4B): : 2611 - 2615
[47] Analysis of a novel self-aligned elevated source drain metal-oxide-semiconductor field-effect transistor with reduced gate-induced drain leakage current and high driving capability
Kim, Kyung-Whan, 2000, JJAP, Tokyo (39):
[48] Analysis of a novel self-aligned elevated source drain metal-oxide-semiconductor field-effect transistor with reduced gate-induced drain leakage current and high driving capability
Kim, KW
Choi, CS
Choi, WY
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (11): : 6208 - 6211
[49] Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain
Ho, Ching-Yuan
Chang, Yaw-Jen
Chiou, Y. L.
JOURNAL OF APPLIED PHYSICS, 2013, 114 (05)
[50] A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
Kow Ming Chang
Yuan Hung Chung
Gin Ming Lin
Jian Hong Lin
Chi Gun Deng
2001, Institute of Electrical and Electronics Engineers Inc. (22)

← 1 2 3 4 5 →