A low-power unified arithmetic unit for programmable handheld 3-D graphics systems

被引：6
|
作者：
Nam, Byeong-Gyu [1 ]
Kim, Hyejung [1 ]
Yoo, Hoi-Jun [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept EECS, 373-1 Guseong Dong, Taejon 305701, South Korea
来源：
PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年
关键词：
D O I：
10.1109/CICC.2006.320921
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-power, area-efficient 128-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3-D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single cycle throughput and the small-size low-power unification of various complex arithmetic operations such as power, logarithm, trigonometric functions, vector multiplication, division, square root and inner product. An uneven 24-piecewise logarithmic conversion scheme is proposed with 0.8% of maximum conversion error. A 93K gate test chip is fabricated with 0.18-mu m CMOS technology. It operates at 210MHz with 15.3mW power consumption at 1.8V.
引用
收藏
页码：535 / 538
页数：4
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