BTI Reliability and Time-Dependent Variability of Stacked Gate-All-Around Si Nanowire Transistors

被引：0

作者：

Chasin, Adrian ^{[1
]}

Franco, Jacopo ^{[1
]}

Kaczer, Ben ^{[1
]}

Putcha, Vamsi ^{[1
,2
]}

Weckx, Pieter ^{[1
]}

Ritzenthaler, Romain ^{[1
]}

Mertens, Hans ^{[1
]}

Horiguchi, Naoto ^{[1
]}

Linten, Dimitri ^{[1
]}

Rzepa, Gerhard ^{[3
]}

机构：

[1] IMEC, Leuven, Belgium

[2] Katholieke Univ Leuven, ESAT, Leuven, Belgium

[3] TU Wien, Vienna, Austria

来源：

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2017年

关键词：

PBTI/NBTI; GAA; FinFETs; time-dependent variability; scaling;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report experimental results of the N/PBTI (Negative/Positive Bias Temperature Instability) reliability of vertically stacked Gate-All-Around (GAA) silicon nanowire (NW) MOSFETs. We benchmark the lifetime of these novel devices against FinFETs with different widths and similar gate-stack. We do not only compare the average degradation, but also the time-dependent variability. At last, we predict the impact of the nanowire diameter on the reliability using TCAD simulations. Both the experimental results and the simulations indicate that BTI reliability is not negatively impacted down to a nanowire diameter of 6nm.

引用

页数：7

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