共 50 条
- [21] A Modified Approach for Reconfigurable FIR Filter Architecture TENCON 2014 - 2014 IEEE REGION 10 CONFERENCE, 2014,
- [23] A Low-Cost Architecture for DWT Filter Banks in RNS Applications 2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 448 - 451
- [24] A NOVEL-APPROACH FOR RESIDUE TO BINARY DECODER FOR RNS FILTER ARCHITECTURE TWENTY-THIRD ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2: CONFERENCE RECORD, 1989, : 878 - 882
- [25] RECONFIGURABLE ARCHITECTURE FOR FIR FILTER WITH LOW POWER CONSUMPTION 2013 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2013, : 1244 - 1249
- [26] Hybrid multiplierless FIR filter architecture based on NEDA VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, 2007, : 316 - 319
- [27] Architecture of a programmable FIR filter co-processor ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : D433 - D436
- [29] Area and delay efficient RNS-based FIR filter design using fast multipliers Measurement: Sensors, 2024, 31
- [30] A new approach to elliptic curve cryptography: An RNS architecture CIRCUITS AND SYSTEMS FOR SIGNAL PROCESSING , INFORMATION AND COMMUNICATION TECHNOLOGIES, AND POWER SOURCES AND SYSTEMS, VOL 1 AND 2, PROCEEDINGS, 2006, : 1241 - 1245