Evaluation and optimization of package processing and design through solder joint profile prediction

被引:19
|
作者
Yeung, BH [1 ]
Lee, TYT [1 ]
机构
[1] Motorola Inc, Semicond Prod Sect, Tempe, AZ 85284 USA
关键词
flip-chip; shape prediction; shape validation; solder design; solder joints; wafer level;
D O I
10.1109/TEPM.2003.812998
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for, applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.
引用
收藏
页码:68 / 74
页数:7
相关论文
共 50 条
  • [31] Investigation and prediction of solder joint failure analysis for ball grid array package subject to mechanical bending environment
    Wu, Mei-Ling
    Lan, Jia-Shen
    SOLDERING & SURFACE MOUNT TECHNOLOGY, 2017, 29 (02) : 75 - 84
  • [32] Prediction on response to the thermal fatigue of through-hole solder joint I. Experimental research of solder joint response to the thermal fatigue
    Ding, Y
    Wang, CQ
    Tian, YH
    ACTA METALLURGICA SINICA, 2003, 39 (08) : 879 - 884
  • [33] Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation
    Shohji, I
    Mori, H
    Orii, Y
    MICROELECTRONICS RELIABILITY, 2004, 44 (02) : 269 - 274
  • [34] Thermal fatigue life evaluation of lead-free solder joint of chip size package with underfill
    Tohei, Tomotake
    Shohji, Ikuo
    Yoshizawa, Keisuke
    Nishimoto, Masaharu
    Kawano, Takayuki
    Mizutani, Yumiko
    Ohsaki, Yoshihiko
    JOURNAL OF THE JAPAN INSTITUTE OF METALS, 2008, 72 (03) : 244 - 248
  • [35] Dual die processor package design optimization and performance evaluation
    Suryakumar, Mahadevan
    Hasan, Altaf
    Phan, Lu-vong
    Sarangi, Ananda
    Fan, Salina
    56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 215 - +
  • [36] Optimization of solder reflow processing and part design in thermoplastic optical interconnect components
    Johnson, Peter M.
    Sugawara, Takamune
    Ohno, Norihiko
    Hoogland, Gabrie
    INTEGRATED OPTICS: DEVICES, MATERIALS, AND TECHNOLOGIES XXIV, 2020, 11283
  • [37] Prediction on response to the thermal fatigue of through-hole solder joint II. Numerical simmulation of mechanical response characteristics of inner solder joint
    Ding, Y
    Wang, CQ
    Tian, YH
    ACTA METALLURGICA SINICA, 2003, 39 (08) : 885 - 891
  • [38] Wafer level and flip chip design through solder prediction models and validation
    Li, L
    Yeung, BH
    IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2001, 24 (04): : 650 - 654
  • [39] A complete software package for transformer design optimization and economic evaluation analysis
    Amoiralis, Eleftherios I.
    Georgilakis, Pavlos S.
    Tsili, Marina A.
    Kladas, Antonios G.
    Souflaris, Athanassios T.
    APPLIED ELECTROMAGNETIC ENGINEERING FOR MAGNETIC, SUPERCONDUCTING AND NANOMATERIALS, 2011, 670 : 535 - +
  • [40] Packaging parameter analysis and optimization design on solder joint reliability for twin die stacked packages by variance in strain energy density (SED) of each solder joint
    Mao, Chao-Yang
    Chen, Rong-Sheng
    MICROELECTRONICS RELIABILITY, 2008, 48 (01) : 119 - 131