Evaluation and optimization of package processing and design through solder joint profile prediction

被引:19
|
作者
Yeung, BH [1 ]
Lee, TYT [1 ]
机构
[1] Motorola Inc, Semicond Prod Sect, Tempe, AZ 85284 USA
关键词
flip-chip; shape prediction; shape validation; solder design; solder joints; wafer level;
D O I
10.1109/TEPM.2003.812998
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for, applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.
引用
收藏
页码:68 / 74
页数:7
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