Evaluation and optimization of package processing, design, and reliability through solder joint profile prediction

被引:2
|
作者
Yeung, BH [1 ]
Lee, TYT [1 ]
机构
[1] Motorola Inc, Interconnect Syst Labs, Tempe, AZ 85284 USA
关键词
D O I
10.1109/ECTC.2001.927906
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, line pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.
引用
收藏
页码:925 / 930
页数:6
相关论文
共 50 条
  • [1] Evaluation and optimization of package processing and design through solder joint profile prediction
    Yeung, BH
    Lee, TYT
    IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2003, 26 (01): : 68 - 74
  • [2] Probabilistic design approach for package design and solder joint reliability optimization for a lead free BGA package
    Limaye, P
    Vandeveld, B
    Van de Peer, J
    Donders, S
    Darveaux, R
    THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS, 2005, : 531 - 537
  • [3] Electromigration failure prediction and reliability evaluation of solder bumps for FCBGA package
    Zhang, Yuanxiang
    Engineering Transactions, 2015, 63 (02): : 215 - 232
  • [4] Extra thin profile land grid array package solder joint reliability assessment
    Wong, Pak Wing
    Ying, Ming
    Tengh, Alfred
    Mohtar, Artnan
    Chia, Yew Choon
    EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 307 - 312
  • [5] Improving WLCSP reliability through solder joint geometry optimization
    1600, IMAPS-International Microelectronics and Packaging Society (41):
  • [6] Parametric Design Study of a Power Electronics Package for Improving Solder Joint Reliability
    Paret, Paul
    DeVoto, Douglas
    Major, Joshua
    Narumanchi, Sreekant
    PROCEEDINGS OF THE NINETEENTH INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS (ITHERM 2020), 2020, : 1065 - 1072
  • [7] Maximizing solder joint reliability through optimal shape design
    Deshpande, AM
    Subbarayan, G
    Mahajan, RL
    JOURNAL OF ELECTRONIC PACKAGING, 1997, 119 (03) : 149 - 155
  • [8] Effect of package design and layout on EGA solder joint reliability of an organic C4 package
    Chandran, B
    Goyal, D
    Thomas, J
    50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1205 - 1214
  • [9] The influence of the solder joint void on the CCGA package reliability
    Huang, Yingzhuo
    Lian, Binhao
    Yao, Quanbin
    Lv, Xiaorui
    Lin, Pengrong
    2014 15TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2014, : 850 - 853
  • [10] The effect of solder joint geometry on electronic package reliability
    Warde, J
    Wallach, ER
    1998 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 1998, 3582 : 808 - 813