Prediction of CMOS transistor performance at 0.10 mu m gate length using tuned simulations

被引：0
|
作者：
Sridhar, S
Mehrotra, M
Rodder, M
Nandakumar, M
Chen, IC
机构：
来源：
MICROELECTRONIC DEVICE TECHNOLOGY | 1997年 / 3212卷
关键词：
0.10 mu m CMOS; tuned simulator; scaled CMOS technology; predictive simulation; MOSFET design;
D O I：
10.1117/12.284594
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Predictive device simulation is essential in order to improve MOSFET design, and reduce development time and costs. In this paper, the results of a simulation study carried out to predict the performance of N and P channel MOSFETs having a physical gate length of 0.10 mu m at supply voltages of 1.2 and 1.5 V are presented. The study was used to determine the feasibility of the FOM [1] goal for scaled 0.10 mu m CMOS, and to identify the values of key device parameters (the external source drain resistance (Rext), poly-gate doping, etc) which would improve device performance.
引用
收藏
页码：208 / 219
页数：12
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