PCA based programmable path signature analysis in BIST

被引:0
|
作者
Zhang, CW [1 ]
Peng, QC [1 ]
Li, YB [1 ]
机构
[1] Univ Elect Sci & Technol China, Inst Commun & Informat Engn, Lab 140, Chengdu 610054, Peoples R China
来源
2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4 | 2002年
关键词
programmable cellular automata (PCA); built-in self-test (BIST); circuit under test (CUT); signature analysis (SA);
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A novel approach of programmable cellular automata (PCA) based switch path signature analysis in built-in self-test (BIST) is presented in this paper. By taking account of the biased output bits of the circuit under test (CUT) while computing aliasing probability, we can obtain lower bound of the aliasing probability contrasting to the former methods such as linear feedback shift register (LFSR) and multiple input shift register (MISR).
引用
收藏
页码:1227 / 1229
页数:3
相关论文
共 50 条
  • [41] A Signature Recognition Technique With a Powerful Verification Mechanism Based on CNN and PCA
    Abosamra, Gibrael
    Oqaibi, Hadi
    IEEE ACCESS, 2024, 12 : 40634 - 40656
  • [42] Unified data path allocation and BIST intrusion
    Olcoz, K
    Tirado, F
    Mecha, H
    INTEGRATION-THE VLSI JOURNAL, 1999, 28 (01) : 55 - 99
  • [43] ESD laboratory simulations and signature analysis of a CMOS programmable logic product
    Henry, LG
    Raymond, T
    Mahanpour, M
    Morgan, I
    MICROELECTRONICS RELIABILITY, 1998, 38 (11) : 1715 - 1721
  • [44] SIGNATURE ANALYSIS AS A MEANS TO OBTAIN ONLINE SAFETY FOR PROGRAMMABLE ELECTRONIC SYSTEMS
    SCHWEITZER, A
    BREMONT, J
    LAMOTTE, M
    ONDE ELECTRIQUE, 1988, 68 (06): : 52 - 58
  • [45] Data Path Management in Mesh-Based Programmable Routers
    Wu, Qiang
    Wolf, Tilman
    2010 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, 2010,
  • [46] BGP path verification mechanism based on sanitizable signature
    Zhao, Chen
    Sun, Bin
    Yang, Yixian
    Yang, Yan
    International Journal of Digital Content Technology and its Applications, 2012, 6 (21) : 274 - 282
  • [47] A high-level data path allocation algorithm based on BIST testability metrics
    Yang, LT
    Muzio, J
    ICM 2002: 14TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2002, : 232 - 236
  • [48] Hybrid BIST based on repeating sequences and cluster analysis
    Li, L
    Chakrabarty, K
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 1142 - 1147
  • [49] A BIST-based charge analysis for embedded memories
    Alorda, B
    Canals, V
    de Paúl, I
    Segura, J
    10TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2004, : 199 - 204
  • [50] Programmable at-speed array and functional BIST for embedded DRAM LSI
    Kume, M
    Uehara, K
    Itakura, M
    Sawamoto, H
    INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 988 - 996