共 50 条
- [1] Register allocation with simultaneous BIST intrusion 24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2, 1998, : 99 - 106
- [2] Redundant transformations for BIST testability metrics-based data path allocation APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2002, : 119 - 123
- [3] A high-level data path allocation algorithm based on BIST testability metrics ICM 2002: 14TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2002, : 232 - 236
- [4] Data path synthesis for BIST with low area overhead PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999, 1999, : 275 - 278
- [5] Data path BIST synthesis with optimized test resources PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN & COMPUTER GRAPHICS, 1999, : 706 - 710
- [6] Allocation Techniques for Reducing BIST Area Overhead of Data Paths Journal of Electronic Testing, 1998, 13 : 149 - 166
- [7] Allocation techniques for reducing BIST area overhead of data paths JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 13 (02): : 149 - 166
- [8] Allocation techniques for reducing BIST area overhead of data paths Journal of Electronic Testing: Theory and Applications (JETTA), 1998, 13 (02): : 149 - 166
- [9] Exploiting test resource optimization in data path synthesis for BIST NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 342 - 343