On the parasitic gate capacitance of small-geometry MOSFETs

被引：4

作者：

Kumar, MJ ^{[1
]}

Venkataraman, V ^{[1
]}

Gupta, SK ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, New Delhi 110016, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2005年 / 52卷 / 07期

关键词：

analytical model; device scaling; MOSFETs; parasitic capacitance;

D O I：

10.1109/TED.2005.850630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

引用

页码：1676 / 1677

页数：2

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