共 50 条
- [31] Secure Scan-based Design Using Blum Blum Shub Algorithm PROCEEDINGS OF 2016 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS), 2016,
- [32] Scan-Based SoC test using space/time pattern compaction schemes DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2006, : 433 - +
- [33] Improved algorithms for constructive multi-phase test point insertion for scan based BIST ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 604 - 611
- [34] INVITED - A Box of Dots: Using Scan-Based Path Delay Test for Timing Verification 2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2016,
- [35] New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure VLSI-SOC: AT THE CROSSROADS OF EMERGING TRENDS, 2015, 461 : 48 - 68
- [36] Transition test generation using replicate-and-reduce transform for scan-based designs 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 22 - 27
- [38] Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs 8TH INTERNATIONAL TEST CONFERENCE IN ASIA, ITC-ASIA 2024, 2024,
- [39] On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 531 - 537
- [40] Test point selection using wavelet transforms for mixed-signal circuits WAVELET APPLICATIONS VII, 2000, 4056 : 275 - 282