Improved algorithms for constructive multi-phase test point insertion for scan based BIST

被引：3
|
作者：
Basturkmen, NZ [1 ]
Reddy, SM [1 ]
Rajski, J [1 ]
机构：
[1] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA
来源：
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ASPDAC.2002.995003
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
New test point selection algorithms to improve test point insertion quality and performance of multi-phase test point insertion scheme, while reducing the memory requirement of the analyses are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy. is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large. industrial circuits demonstrate the effectiveness of the new algorithms.
引用
收藏
页码：604 / 611
页数：2
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