Recent Findings In Electrical Behavior Of CMOS High-k Dielectric/Metal Gate Stacks

We first review the kinetics of the trapping/detrapping process involved in hysteresis phenomena of HfO2 films on a large temperature range (20K-500K). We show that, up to 400K, trapping and detrapping processes are temperature independent after correction of threshold voltage variation with temperature. In most cases, the capture and emission into or from available traps are mainly controlled by tunneling. Then, we address the variations of the effective metal work function and its relation with the different fabrication processes. Based on C-V and internal photoemission measurements, we show the existence of an interfacial voltage drop (i.e. dipole) at the high-k SiO2 interface, as well as of variations in metal work function with metal gate process. Finally, we present a complete study of the transport mechanisms throughout the SiO2/HfO2 gate stacks combining C-V, I-V and Transmission Electron Microscopy measurements, on several nMOS transistors with different interfacial layer and HfO2 thicknesses, over a large temperature range (80K to 400K).