Fault simulation of behavioral VHDL model

The behavioral VHDL (VHSIC Description Language) model of digital circuit is an algorithm shaped into concurrent processes they communicate by signals. The problem of ATPG (Automatic Test Pattern Generation) is to construct a method for diagnostics of such behavioral model. The diagnostics is based on incorporation of fault model, where a set of all possible faults is applied into given VHDL model and a minimal set of test patterns is investigated to detect as much faults as possible handling the behavioral model of digital circuit as a black box. This paper reports about the fault simulation algorithm, its implementation and connection to the whole ATPG system at the VHDL behavioral level of circuit description. Similar experiments are known in past at the gate level of digital circuits. The behavioral level diagnostics may be close to diagnostics of other systems then VHDL models.