RC power bus maximum voltage drop in digital VLSI circuits

被引：3
|
作者：
Bai, G [1 ]
Bobba, S [1 ]
Hajj, IN [1 ]
机构：
[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA
来源：
INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ISQED.2001.915238
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an inp ut-independent method for finding bounds on the voltage drop in RC power bus in digital VLSI circuits. The voltage at power bus nodes is expressed in term of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous HL and LH switching in a clock subinterval. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes.
引用
收藏
页码：257 / 258
页数：2
相关论文
共 50 条
  • [1] RC power bus maximum voltage drop in digital VLSI circuits
    Bai, G
    Bobba, S
    Hajj, IN
    INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2001, : 205 - 210
  • [2] Bus architecture for low-power VLSI digital circuits
    Cardarilli, GC
    Salmeri, M
    Salsano, A
    Simonelli, O
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 21 - 24
  • [3] Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
    Bobba, S
    Hajj, IN
    ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, : 376 - 381
  • [4] Approaches for reducing power consumption in VLSI bus circuits
    Asada, Kunihiro
    Ikeda, Makoto
    Komatsu, Satoshi
    IEICE Transactions on Electronics, 2000, E83-C (02) : 153 - 160
  • [5] Approaches for reducing power consumption in VLSI bus circuits
    Asada, K
    Ikeda, M
    Komatsu, S
    IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (02): : 153 - 160
  • [6] Estimation of maximum switching activity in digital VLSI circuits
    Bobba, S
    Hajj, IN
    40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 1130 - 1133
  • [7] Derivation of the maximum voltage drop in power grids of integrated circuits with an array bonding package
    Aguareles, M.
    de Haro, J.
    EUROPEAN JOURNAL OF APPLIED MATHEMATICS, 2012, 23 : 797 - 819
  • [8] Effects of delay models on maximum power estimation of VLSI circuits
    Lu, JM
    Lin, ZG
    2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 179 - 182
  • [9] New statistical method for maximum power estimation in CMOS VLSI circuits
    Evmorfopoulos, N.E.
    Avaritsiotis, J.N.
    Active and Passive Electronic Components, 2000, 22 (03) : 215 - 233
  • [10] Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems
    Nan, Yang
    Zhan, Chenchang
    Wang, Guanhua
    He, Linjun
    Li, Han
    2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 6 - 9
12345