RC power bus maximum voltage drop in digital VLSI circuits

被引：3
|
作者：
Bai, G [1 ]
Bobba, S [1 ]
Hajj, IN [1 ]
机构：
[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA
来源：
INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ISQED.2001.915238
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an inp ut-independent method for finding bounds on the voltage drop in RC power bus in digital VLSI circuits. The voltage at power bus nodes is expressed in term of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous HL and LH switching in a clock subinterval. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes.
引用
收藏
页码：257 / 258
页数：2
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