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- [21] Electron beam lithography simulation based on a single convolution approach - Application for sub-45 nm nodes EMLC 2007: 23RD EUROPEAN MASK AND LITHOGRAPHY CONFERENCE, 2007, 6533
- [24] Fifteen-Nanometer Ru Diffusion Barrier on NiSi/Si for a sub-45 nm Cu Contact Plug Journal of Electronic Materials, 2009, 38 : 2251 - 2256
- [25] ESD Protection Using Grounded Gate, Gate Non-Silicided (GG-GNS) ESD NFETs in 45nm SOI Technology ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008, 2008, : 312 - 316
- [27] Correction for Surface Charge Induced Beam Displacement in Large Area Sub-45 nm Patterning with FIB Lithography LITHOGRAPHY ASIA 2008, 2008, 7140
- [28] ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1182 - 1185
- [29] Image placement error of photomask due to pattern loading effect: analysis and correction technique for sub-45 nm node PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XV, PTS 1 AND 2, 2008, 7028
- [30] A new process and tool for metal/high-k gate dielectric stack for sub-45 nm CMOS manufacturing ISSM 2007: 2007 INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2007, : 493 - +