A high speed efficient N X N bit multiplier based on ancient Indian vedic mathematics

A N X N high, speed, efficient fully synthesizable multiplier based on algorithm of ancient Indian Mathematics called Vedic Mathematics [1] is presented in this paper. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsis FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -6. The design is completely technology independent and can be easily converted from one technology to another. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication algorithm implemented in coprocessors. In FPGA implementation it has been found that Vedic multiplier is faster than array multiplier.