POWER8 Design Methodology Innovations for Improving Productivity and Reducing Power

被引:0
|
作者
Ziegler, Matthew M. [1 ]
Puri, Ruchir [1 ]
Philhower, Bob [1 ]
Franch, Robert [1 ]
Luk, Wing [1 ]
Leenstra, Jens [2 ]
Verwegen, Peter [2 ]
Fricke, Niels [2 ]
Gristede, George [1 ]
Fluhr, Eric [3 ]
Zyuban, Victor [1 ]
机构
[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] IBM Corp, Syst & Technol Grp, Boblingen, Germany
[3] IBM Corp, Syst & Technol Grp, Austin, TX USA
关键词
Design methodology; low power design; synthesis; processors; servers;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.
引用
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页数:9
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