Some initial explorations into the hierarchical multi-core chip design space for HPC systems

Multi-core designs have emerged as the dominant trend for commodity and high performance microprocessor chips, in virtually all market segments. This includes the high performance supercomputing arena. Using a particular HPC system as a baseline, this paper performs some initial explorations of how the constraints of chip technology, system-imposed memory and bandwidth, and application characteristics may govern the performance achievable from future HPC systems.