Some initial explorations into the hierarchical multi-core chip design space for HPC systems

被引：1
|
作者：
Kogge, Peter M. [1 ]
机构：
[1] Univ Notre Dame, Notre Dame, IN 46556 USA
来源：
INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS | 2007年
关键词：
D O I：
10.1109/IWIA.2007.9
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Multi-core designs have emerged as the dominant trend for commodity and high performance microprocessor chips, in virtually all market segments. This includes the high performance supercomputing arena. Using a particular HPC system as a baseline, this paper performs some initial explorations of how the constraints of chip technology, system-imposed memory and bandwidth, and application characteristics may govern the performance achievable from future HPC systems.
引用
收藏
页码：3 / 10
页数：8
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