共 50 条
- [2] Low-power low-noise CMOS analogue multiplier IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (03): : 261 - 267
- [3] Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications IEICE ELECTRONICS EXPRESS, 2018, 15 (03):
- [6] Multiplier Structures for Low Power Applications in Deep-CMOS 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1061 - 1064
- [7] Low Power Optimized Array Multiplier with Reduced Area HIGH PERFORMANCE ARCHITECTURE AND GRID COMPUTING, 2011, 169 : 224 - +
- [8] Low Power & Area Multiplier for Deep Learning Applications BIOSCIENCE BIOTECHNOLOGY RESEARCH COMMUNICATIONS, 2020, 13 (14): : 448 - 451