Low Power and Low Area CMOS Capacitance Multiplier

被引：0

作者：

Bonteanu, Gabriel ^{[1
]}

Cracan, Arcadie ^{[1
]}

机构：

[1] Gheorghe Asachi Tech Univ Iasi, Iasi, Romania

来源：

CAS 2018 PROCEEDINGS: 2018 INTERNATIONAL SEMICONDUCTOR CONFERENCE | 2018年

关键词：

MOS capacitor; capacitance multiplier; adjustable capacitor; low power; relaxation oscillator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power and low area voltage mode CMOS capacitance multiplication technique is presented. The multiplication factor is conveniently given by the transconductance ratio of two transistors, thereby improving the immunity to process and temperature variations. A low power wide range adjustable relaxation oscillator is presented as application.

引用

页码：161 / 164

页数：4

共 50 条

[31] A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers
Faisal, Md Ibrahim
Bayoumi, Magdy A.
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 1460 - 1463
[32] CMOS preamplifier for low-capacitance detectors
Gramegna, G
OConnor, P
Rehak, P
Hart, S
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 1997, 390 (1-2): : 241 - 250
[33] Low power-four quadrant CMOS analog multiplier for artificial neural networks
Kapanoglu, B
Yildirim, T
PROCEEDINGS OF THE IEEE 12TH SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE, 2004, : 137 - 139
[34] CMOS design of a low power and high precision four-quadrant analog multiplier
Beyraghi, Naser
Khoei, Abdollah
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2015, 69 (01) : 400 - 407
[35] Device and circuit level analysis of negative capacitance hybrid CMOS: a prospect for low power/low voltage applications
Bansal, Monika
Kaur, Harsupreet
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (01)
[36] Low power small area modified booth multiplier design for predetermined coefficients
Kim, Yong-Eun
Cho, Kyung-Ju
Chung, Jin-Gyun
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2007, E90A (03) : 694 - 697
[37] Low-power and Area Efficient Approximate Multiplier with Reduced Partial Products
Sukla, Mukesh Kumar
Sethi, Kabiraj
Panda, A. K.
PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2020), 2020, : 181 - 186
[38] A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier
Sawigun, Chutham
Demosthenous, Andreas
Pal, Dipankar
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 751 - +
[39] A low voltage CMOS multiplier for high frequency equalization
Abbott, J
Plett, C
Rogers, JWM
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1936 - 1939
[40] A low-voltage CMOS multiplier for RF applications
Debono, CJ
Maloberti, F
Micallef, J
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 225 - 227

← 1 2 3 4 5 →