A 10-bit 1 MS/s 3-step ADC with bitstream-based sub-dac and sub-ADC calibration

被引：0
|
作者：
Pishdad, B [1 ]
Roberts, GW [1 ]
机构：
[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 2T5, Canada
来源：
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 3-step, Nyquist-rate ADC is presented which makes use of bitstream techniques to design and calibrate the D/A subconverter, while using the same hardware to calibrate the A/D subconverter. The novel methods presented remove the dependence on offsets and component mismatches in the D/A subconverter. They eliminate the need for a reference ladder in the A/D subconverter and calibrate comparator offsets. In addition, DC offsets in the residue amplifier are calibrated. Simulation results of a prototype in 0.18mu CMOS technology show 10 bits of resolution at an operating speed of 1 MS/s.
引用
收藏
页码：501 / 504
页数：4
相关论文
共 50 条
  • [31] A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS
    Liang, Yuhua
    Zhu, Zhangming
    Ding, Ruixue
    MICROELECTRONICS JOURNAL, 2015, 46 (10) : 988 - 995
  • [32] A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration
    Choi, Yongsuk
    Kim, Yong-Bin
    Jung, In-Seok
    2016 IEEE 25TH NORTH ATLANTIC TEST WORKSHOP (NATW), 2016, : 1 - 5
  • [33] A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
    Verma, Deeksha
    Shehzad, Khuram
    Khan, Danial
    Kim, Sung Jin
    Pu, Young Gun
    Yoo, Sang-Sun
    Hwang, Keum Cheol
    Yang, Youngoo
    Lee, Kang-Yoon
    ELECTRONICS, 2020, 9 (07) : 1 - 11
  • [34] A Low-Power 10-bit 50-MS/s SAR ADC Using a Parasitic-Compensated Split-Capacitor DAC
    Guo, Wei
    Mirabbasi, Shahriar
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1275 - 1278
  • [35] A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS
    Li, Dengquan
    Zhu, Zhangming
    Ding, Ruixue
    Yang, Yintang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (11) : 1524 - 1528
  • [36] A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier
    Lee, Han-Yeol
    Youn, Eunji
    Jang, Young-Chan
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2019, 19 (04) : 378 - 387
  • [37] A 10-bit40-MS/s Time-Domain Two-Step ADC With Short Calibration Time
    Chen, Liang-Jen
    Liu, Shen-Iuan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (02) : 126 - 130
  • [38] Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC
    Zhu, Yan
    Chan, Chi-Hang
    Wong, Si-Seng
    Seng-Pan, U.
    Martins, Rui Paulo
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (03) : 1203 - 1207
  • [39] A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing
    Wang, Cheng
    Yang, Zhanpeng
    Xing, Xinpeng
    Duan, Quanzhen
    Zheng, Xinfa
    Gielen, Georges
    ELECTRONICS, 2023, 12 (19)
  • [40] An embedded 170-mW 10-bit 50-MS/s CMOS ADC in 1-mm2
    Bult, K
    Buchwald, A
    ANALOG CIRCUIT DESIGN: RF ANALOG-TO-DIGITAL CONVERTERS; SENSOR AND ACTUATOR INTERFACES; LOW-NOISE OSCILLATORS, PLLS AND SYNTHESIZERS, 1997, : 49 - 63
12345