FPGA implementation of a scalable shared buffer ATM switch

被引：1

作者：

Shim, JW ^{[1
]}

Jeong, GJ ^{[1
]}

Lee, MK ^{[1
]}

Ahn, SH ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect Engn, Seodaemun Ku, Seoul 120749, South Korea

来源：

ICAATM'98: 1998 1ST IEEE INTERNATIONAL CONFERENCE ON ATM | 1998年

关键词：

FPGA; shared buffer; scalability;

D O I：

10.1109/ICATM.1998.688184

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the architecture of a scalable shared buffer ATM switch and FPGA implementation. The proposed ATM switch has 2-D array of sub-memory block as shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for 4x4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of designed test-bed is 40MHz.

引用

页码：247 / 251

页数：5

共 50 条

[31] Performance study of buffer control schemes and cell discard mechanisms in a shared buffer ATM switch
Dou, C
Sheu, JS
IEICE TRANSACTIONS ON COMMUNICATIONS, 1998, E81B (05) : 899 - 909
[32] Methods for storing arriving cells in a shared multi-buffer ATM switch
Shibata, A
Inai, H
Yamakita, J
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS, 1999, 82 (02): : 39 - 47
[33] Performance analysis of shared buffer ATM switch with different cell departure models
Fong, S
Singh, S
1998 IEEE INTERNATIONAL PERFORMANCE, COMPUTING AND COMMUNICATIONS CONFERENCE, 1997, : 386 - 392
[34] An approximate analysis of a shared buffer ATM switch using input process aggregation
Kim, J
Jun, CH
IEICE TRANSACTIONS ON COMMUNICATIONS, 1999, E82B (12) : 2107 - 2115
[35] An approximate transient analysis of dynamic thresholds in an ATM switch with shared buffer memory
Zouta, T
Inai, H
Yamakita, J
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS, 2001, 84 (06): : 1 - 10
[36] Performance of an ATM multi-stage shared buffer switch with broadcast traffic
Raffaelli, C
Casoni, M
ATM, NETWORKS AND LANS - NOC '96-II, 1996, : 130 - 137
[37] Throughput enhancement of shared multi-buffer ATM switch in multicast environments
Lee, JI
Sohn, JM
Lee, MK
IEICE TRANSACTIONS ON COMMUNICATIONS, 1999, E82B (12) : 2153 - 2159
[38] Methods for storing arriving cells in a shared multi-buffer ATM switch
Shibata, Atsushi
Inai, Hiroshi
Yamakita, Jiro
Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 1999, 82 (02): : 39 - 47
[39] A CAM-based VLSI architecture for shared buffer ATM switch with fuzzy controlled buffer management
Dou, C
Shieh, MD
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 149 - 152
[40] Design and implementation of an ABR server in a shared-bus ATM switch
Zervanos, E.
Stassinopoulos, G.
IEEE Symposium on Computers and Communications - Proceedings, 2000, : 366 - 371

← 1 2 3 4 5 →