FPGA implementation of a scalable shared buffer ATM switch

被引：1

作者：

Shim, JW ^{[1
]}

Jeong, GJ ^{[1
]}

Lee, MK ^{[1
]}

Ahn, SH ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect Engn, Seodaemun Ku, Seoul 120749, South Korea

来源：

ICAATM'98: 1998 1ST IEEE INTERNATIONAL CONFERENCE ON ATM | 1998年

关键词：

FPGA; shared buffer; scalability;

D O I：

10.1109/ICATM.1998.688184

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the architecture of a scalable shared buffer ATM switch and FPGA implementation. The proposed ATM switch has 2-D array of sub-memory block as shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for 4x4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of designed test-bed is 40MHz.

引用

页码：247 / 251

页数：5

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