A Verification of Resonant Clock Driver Design for the IoT Era

被引：0

作者：

Takahashi, Yasuhiro ^{[1
]}

Sekine, Toshikazu ^{[1
]}

Yokoyama, Michio ^{[2
]}

机构：

[1] Gifu Univ, Fac Engn, Dept Elect Elect & Comp Engn, 1-1 Yanagido, Gifu 5011193, Japan

[2] Yamagata Univ, Grad Sch Sci & Engn, 4-3-16 Jonan, Yonezawa, Yamagata 9928510, Japan

来源：

2017 12TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT) | 2017年

关键词：

FREQUENCY; EFFICIENT; CIRCUITS; LOGIC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we simulate a resonant clocking driver for low power and low-voltage LSI. During the past decade, several highspeed LSI test chips operating in GHz range successfully demonstrated a variety of resonant clocking implementations, but few tests in low-frequency range have been reported. The authors report the operation of the low operating frequency resonant clock driver for IoT device through the SPICE simulation. From the simulation results, we found that the aspect ratio (W/L) of MOS in the final stage is the important geometrical factor that determines the clock waveform.

引用

页码：268 / 270

页数：3

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