A Verification of Resonant Clock Driver Design for the IoT Era

In this paper, we simulate a resonant clocking driver for low power and low-voltage LSI. During the past decade, several highspeed LSI test chips operating in GHz range successfully demonstrated a variety of resonant clocking implementations, but few tests in low-frequency range have been reported. The authors report the operation of the low operating frequency resonant clock driver for IoT device through the SPICE simulation. From the simulation results, we found that the aspect ratio (W/L) of MOS in the final stage is the important geometrical factor that determines the clock waveform.