Adaptive decision-feedback equalization for band-limited high-speed serial links

A high-speed I/O cell comprising a mixed-signal 8-tap decision-feedback equalizer (DFE) with direct cancellation of the first post-cursor inter-symbol interference (ISI) has been implemented in 0.13-mu m CMOS technology. Based on a joint optimization of algorithms and architecture a low-complexity architecture has been chosen with respect to a compromise between ISI reduction and implementation complexity. The I/O cell dissipates only 86 mW at the target rate of 6.4 Gbps. It is the core of a high-speed I/O link with adaptive receiver equalization. Due to the residual ISI the adaptation algorithm has to be modified. The concept has been analyzed by system simulations and verified by measurements of the implemented I/O link.