7Gbit/s measurements on a 0.8μm CMOS line-receiver

被引：0
|
作者：
Johansson, HO [1 ]
机构：
[1] Linkoping Univ, Dept Phys & Measurement Technol, S-58183 Linkoping, Sweden
来源：
ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Successful sampling of every 32nd bit in a 7-Gbit/s data stream has been shown with a 0.8-mu m CMOS circuit which is based on parallel sampling. The input bandwidth of the chip is the suspected bit rate limiting factor. The input bandwidth is mainly set by the wire characteristic impedance and the input capacitance of the chip. Half of a 5-Gbit/s data stream has been received by the same circuit. This indicates that (full) reception of 5-Gbit/s data-streams is possible. The bit rate limiting factor in this case is the accuracy and jitter of the control-clocks to the sampling-switches.
引用
收藏
页码：A308 / A311
页数：4
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