Reconfigurable Architecture of a Pulse Shaping FIR Filter for Multistandard DUC

As the technology is progressing with increasing time, so is the requirement for more portable and power efficient devices. FIR filters play a very important role in telecommunications, especially for applications like channelization, matched filtering, etc. Nowadays, many communication standards are present, and designing an FIR filter for each of these standards with different parameters consumes a lot of area and power. Also, while transmitting a signal, it can become distorted due to interferences and channel bandwidth limitations. The major cause of distortion occurs due to Inter-symbol Interference and can lead to aliasing and loss of important data. Hence, we need a pulse shaping filter to overcome these interferences. This paper proposes a reconfigurable pulse shaping FIR interpolator filter for a multistandard Digital Upconverter (DUC). The major complexity of FIR filters is due to coefficient multiplication. By reducing the no. of multipliers as well as adders in an FIR filter, both its power and area can be reduced. In this paper, two steps have been implemented to minimize the no. of additions as well as multiplications. In the first step, the no. of multiplications and additions required per input sample has been reduced. In the following step, 2 bit binary common subexpression based elimination (BCSE) algorithm has been implemented. Furthermore, the speed of operation of the filter has been increased by reducing the path delay of the filter. The architecture consists of four building blocks; Data Generator, Coefficient Generator, Processing Block and Accumulation Unit. The filter has been designed using Verilog and synthesized in Xilinx ISE Editor 14.2.