AN OPTIMIZED ARCHITECTURE FOR DYNAMIC RECONFIGURABLE FIR FILTER IN SPEECH PROCESSING

In this paper, we have proposed a Dynamic Reconfiguration Scheme (DRS) for the FIR filter in which the existing multiplier of the FIR filter is replaced by the proposed Estimation Distribution Multiplier Blocks (EDMB). The important aspect of the proposed DRS is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposed method and to further evaluate the performance and correctness of the structure in terms of area and power consumption, we have implemented the hardware in Xilinx Virtex 7 Field Programmable Gate Array (FPGA) device and synthesized with Cadence RTL Compiler using TSMC 180 nm standard cell library. The experimental analysis of the proposed reconfigurable design approach takes speech signal as the benchmark input. The analysis shows that the proposed technique is better when compared to the existing reconfiguration techniques with 43.60% power savings and 6.34% area reduction.