An efficient bus architecture for system-on-chip design

被引：26
|
作者：
Cordan, B [1 ]
机构：
[1] PALMCHIP Corp, Colorado Design Ctr, Loveland, CO USA
来源：
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年
关键词：
D O I：
10.1109/CICC.1999.777358
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the issues confronted when integrating system-on-chip (SOC) designs and offers solution through a detailed description of the CoreFrame(TM) system-on-chip bus architecture that has dramatically reduce system design and verification effort while enhancing the reusability and customizability of system-on-chip product developments. The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance.
引用
收藏
页码：623 / 626
页数：4
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