Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates

被引：0

作者：

Mertens, H. ^{[1
]}

Ritzenthaler, R. ^{[1
]}

Hikavyy, A. ^{[1
]}

Kim, M. S. ^{[1
]}

Tao, Z. ^{[1
]}

Wostyn, K. ^{[1
]}

Chew, S. A. ^{[1
]}

De Keersgieter, A. ^{[1
]}

Mannaert, G. ^{[1
]}

Rosseel, E. ^{[1
]}

Schram, T. ^{[1
]}

Devriendt, K. ^{[1
]}

Tsvetanova, D. ^{[1
]}

Dekkers, H. ^{[1
]}

Demuynck, S. ^{[1
]}

Chasin, A. ^{[1
]}

Van Besien, E. ^{[1
]}

Dangol, A. ^{[1
]}

Godny, S. ^{[1
]}

Douhard, B. ^{[1
]}

Bosman, N. ^{[1
]}

Richard, O. ^{[1
]}

Geypen, J. ^{[1
]}

Bender, H. ^{[1
]}

Barla, K. ^{[1
]}

Mocuta, D. ^{[1
]}

Horiguchi, N. ^{[1
]}

Thean, A. V-Y ^{[1
]}

机构：

[1] Imec, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for L-G = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

引用

页数：2

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